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ds05-20882-2e fujitsu semiconductor data sheet flash memory cmos 64m (4m 16) bit mbm29lv650ue/651ue -90/12 n n n n description the mbm29lv650ue/651ue is a 64m-bit, 3.0 v-only flash memory organized as 4m words of 16 bits each. the device is designed to be programmed in system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29lv650ue/651ue is entirely command set compatible with jedec single-power-supply flash stan- dard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. typically, each sector can be programmed and verified in about 0.5 seconds. (continued) n n n n product lineup n n n n packages part no. mbm29lv650ue/651ue ordering part no. v cc = 3.3 v 90 v cc = 3.0 v 12 max. address access time (ns) 90 120 max. ce access time (ns) 90 120 max. oe access time (ns) 35 50 +0.3 v C0.3 v +0.6 v C0.3 v (fpt-48p-m20) (fpt-48p-m19) marking side marking side 48-pin plastic tsop (i)
mbm29lv650ue/651ue- 90/12 2 (continued) a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv650ue/651ue is erased when shipped from the factory. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 . once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. the devices electrically erase all bits within a sector simultaneously via fowler-nordhiem tunneling. the words are programmed one word at a time using the eprom programming mechanism of hot electron injection. n n n n features ?0.23 m m process technology ? single 3.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standards uses same software commands with single-power supply flash ? address dont care during the command sequence ? industry-standard pinouts 48-pin tsop (i) (package suffix: tn - normal bend type, tr - reversed bend type) ? minimum 100,000 program/erase cycles ? high performance 90 ns maximum access time ? flexible sector architecture one hundred twenty-eight 32k word sectors any combination of sectors can be concurrently erased. also supports full chip erase ? hidden rom (hi-rom) region 128 word of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp input pin at v il , allows protection of first or last 32k word sector, regardless of sector protection/unprotection status at v ih , allows removal of protection mbm29lv650ue: has the function to protect the last 32k word sector (sa 127) mbm29lv651ue: has the function to protect the first 32k word sector (sa 0) ? acc input pin at v acc , increases program performance ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations (continued)
mbm29lv650ue/651ue- 90/12 3 (continued) ? sector group protection set function by extended sector protect command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin this feature allows code changes in previously locked sectors ? in accordance with cfi (c ommon f lash memory i nterface) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29lv650ue/651ue- 90/12 4 n n n n pin assignments a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 21 a 20 we reset acc wp a 19 a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mbm29lv650ue/651ue standard pinout mbm29lv650ue/651ue reverse pinout tsop(i) a 16 v cc q v ss dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 v ss v cc q a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 a 19 wp acc reset we a 20 a 21 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side) (marking side) fpt-48p-m19 fpt-48p-m20
mbm29lv650ue/651ue- 90/12 5 n n n n pin description table1 mbm29lv650ue/651ue pin configuration pin function a 0 to a 21 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable wp hardware write protection reset hardware reset pin/temporary sector group unprotection acc program acceleration v cc q output buffer power v ss device ground v cc device power supply
mbm29lv650ue/651ue- 90/12 6 n n n n block diagram v ss v cc we ce a 0 to a 21 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch stb stb reset wp timer for program/erase acc v cc q input/output buffers
mbm29lv650ue/651ue- 90/12 7 n n n n logic symbol 22 a 0 to a 21 we oe ce dq 0 to dq 15 16 reset acc wp v cc q
mbm29lv650ue/651ue- 90/12 8 n n n n device bus operation legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 3. 2. refer to the section on sector group protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. v cc = 3.3 v 10% 5. it is also used for the extended sector group protection. table2 mbm29lv650ue/651ue user bus operations operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset wp auto-select manufacture code (1) l l h l l l v id code h x auto-select device code (1) l l h h l l v id code h x read (3) l l h a 0 a 1 a 6 a 9 d out hx standby hxxxxxx high-z h x output disable lhhxxxx high-z h x write (program/erase) l h l a 0 a 1 a 6 a 9 d in hx enable sector group protection (2), (4) l v id lhlv id xhx verify sector group protection (2), (4) l l h l h l v id code h x temporary sector group unprotection (5) x x x x x x x x v id x reset (hardware)/standby xxxxxxx high-z l x outermost sector write protection x x x x x x x x x l
mbm29lv650ue/651ue- 90/12 9 *1: this command is valid while fast mode. *2: this command is valid while reset = v id . *3: the valid addresses are a 6 to a 0 . *4: this command is valid while hi-rom mode. note:1. address bits = x = h or l for all address commands except or program address (pa) and sector address (sa). 2.bus operations are defined in table 2. 3.ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 21 , a 20 , a 19 , a 18 , a 17 ,a 16 , and a 15 will uniquely select any sector. 4.rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5.spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6.both read/reset commands are functionally equivalent, resetting the device to the read mode. table 3 mbm29lv650ue/651ue command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1xxxhf0h read/reset 3 xxxh aah xxxh 55h xxxh f0h ra rd autoselect 3 xxxh aah xxxh 55h xxxh 90h program 4 xxxh aah xxxh 55h xxxh a0h pa pd chip erase 6 xxxh aah xxxh 55h xxxh 80h xxxh aah xxxh 55h xxxh 10h sector erase 6 xxxh aah xxxh 55h xxxh 80h xxxh aah xxxh 55h sa 30h erase suspend 1xxxhb0h erase resume 1xxxh30h set to fast mode 3 xxxh aah xxxh 55h xxxh 20h fast program *12xxxha0hpapd reset from fast mode *1 2xxxh90hxxxhf0h extended sector group protection *2 4xxxh60hspa60hspa40hspasd query *3 1xxh98h hi-rom entry 3 xxxh aah xxxh 55h xxxh 88h hi-rom program *4 4 xxxh aah xxxh 55h xxxh a0h pa pd hi-romexit *4 4 xxxh aah xxxh 55h xxxh 90h xxxh 00h
mbm29lv650ue/651ue- 90/12 10 *: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. table 4 .1 mbm29lv650ue/651ue sector group protection verify autoselect codes type a 17 to a 21 a 6 a 1 a 0 code (hex) manufacturers code x v il v il v il 04h device code mbm29lv650ue/651ue x v il v il v ih 22d7h sector group protection sector group addresses v il v ih v il 01h * extended code mbm29lv650ue xv il v ih v ih 0010h mbm29lv651ue 0000h table 4 .2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04 h0000000000000100 device code mbm29lv650ue/ 651ue 22d7 h0010001011010111 sector group protection 01 h0000000000000001 extend code mbm29lv650ue 0010 h0000000000010000 mbm29lv651ue 0000 h0000000000000000
mbm29lv650ue/651ue- 90/12 11 n n n n flexible sector-erase architecture (continued) table 5 sector address tables sector address a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size address range sa0 0000000 32k words 000000h to 007fffh sa1 0000001 32k words 0 08000h to 00ffffh sa2 0000010 32k words 010000h to 017fffh sa3 0000011 32k words 0 18000h to 01ffffh sa4 0000100 32k words 020000h to 027fffh sa5 0000101 32k words 0 28000h to 02ffffh sa6 0000110 32k words 030000h to 037fffh sa7 0000111 32k words 0 38000h to 03ffffh sa8 0001000 32k words 040000h to 047fffh sa9 0001001 32k words 0 48000h to 04ffffh sa10 0001010 32k words 050000h to 057fffh sa11 0001011 32k words 0 58000h to 05ffffh sa12 0001100 32k words 060000h to 067fffh sa13 0001101 32k words 0 68000h to 06ffffh sa14 0001110 32k words 070000h to 077fffh sa15 0001111 32k words 0 78000h to 07ffffh sa16 0010000 32k words 080000h to 087fffh sa17 0010001 32k words 0 88000h to 08ffffh sa18 0010010 32k words 090000h to 097fffh sa19 0010011 32k words 0 98000h to 09ffffh sa20 0010100 32k words 0a00 00h to 0a7fffh sa21 0010101 32k words 0a8000h to 0affffh sa22 0010110 32k words 0b00 00h to 0b7fffh sa23 0010111 32k words 0b8000h to 0bffffh sa24 0011000 32k words 0c00 00h to 0c7fffh sa25 0011001 32k words 0c8000h to 0cffffh sa26 0011010 32k words 0d00 00h to 0d7fffh sa27 0011011 32k words 0d8000h to 0dffffh sa28 0011100 32k words 0e00 00h to 0e7fffh sa29 0011101 32k words 0e8000h to 0effffh sa30 0011110 32k words 0f00 00h to 0f7fffh sa31 0011111 32k words 0f8000h to 0fffffh
mbm29lv650ue/651ue- 90/12 12 (continued) (continued) sector address a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size address range sa32 0100000 32k words 100000h to 107fffh sa33 0100001 32k words 1 08000h to 10ffffh sa34 0100010 32k words 110000h to 117fffh sa35 0100011 32k words 1 18000h to 11ffffh sa36 0100100 32k words 120000h to 127fffh sa37 0100101 32k words 1 28000h to 12ffffh sa38 0100110 32k words 130000h to 137fffh sa39 0100111 32k words 1 38000h to 13ffffh sa40 0101000 32k words 140000h to 147fffh sa41 0101001 32k words 1 48000h to 14ffffh sa42 0101010 32k words 150000h to 157fffh sa43 0101011 32k words 1 58000h to 15ffffh sa44 0101100 32k words 160000h to 167fffh sa45 0101101 32k words 1 68000h to 16ffffh sa46 0101110 32k words 170000h to 177fffh sa47 0101111 32k words 1 78000h to 17ffffh sa48 0110000 32k words 180000h to 187fffh sa49 0110001 32k words 1 88000h to 18ffffh sa50 0110010 32k words 190000h to 197fffh sa51 0110011 32k words 1 98000h to 19ffffh sa52 0110100 32k words 1a00 00h to 1a7fffh sa53 0110101 32k words 1a8000h to 1affffh sa54 0110110 32k words 1b00 00h to 1b7fffh sa55 0110111 32k words 1b8000h to 1bffffh sa56 0111000 32k words 1c00 00h to 1c7fffh sa57 0111001 32k words 1c8000h to 1cffffh sa58 0111010 32k words 1d00 00h to 1d7fffh sa59 0111011 32k words 1d8000h to 1dffffh sa60 0111100 32k words 1e00 00h to 1e7fffh sa61 0111101 32k words 1e8000h to 1effffh sa62 0111110 32k words 1f00 00h to 1f7fffh sa63 0111111 32k words 1f8000h to 1fffffh
mbm29lv650ue/651ue- 90/12 13 (continued) (continued) sector address a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size address range sa64 1000000 32k words 200000h to 207fffh sa65 1000001 32k words 2 08000h to 20ffffh sa66 1000010 32k words 210000h to 217fffh sa67 1000011 32k words 2 18000h to 21ffffh sa68 1000100 32k words 220000h to 227fffh sa69 1000101 32k words 2 28000h to 22ffffh sa70 1000110 32k words 230000h to 237fffh sa71 1000111 32k words 2 38000h to 23ffffh sa72 1001000 32k words 240000h to 247fffh sa73 1001001 32k words 2 48000h to 24ffffh sa74 1001010 32k words 250000h to 257fffh sa75 1001011 32k words 2 58000h to 25ffffh sa76 1001100 32k words 260000h to 267fffh sa77 1001101 32k words 2 68000h to 26ffffh sa78 1001110 32k words 270000h to 277fffh sa79 1001111 32k words 2 78000h to 27ffffh sa80 1010000 32k words 280000h to 287fffh sa81 1010001 32k words 2 88000h to 28ffffh sa82 1010010 32k words 290000h to 297fffh sa83 1010011 32k words 2 98000h to 29ffffh sa84 1010100 32k words 2a00 00h to 2a7fffh sa85 1010101 32k words 2a8000h to 2affffh sa86 1010110 32k words 2b00 00h to 2b7fffh sa87 1010111 32k words 2b8000h to 2bffffh sa88 1011000 32k words 2c00 00h to 2c7fffh sa89 1011001 32k words 2c8000h to 2cffffh sa90 1011010 32k words 2d00 00h to 2d7fffh sa91 1011011 32k words 2d8000h to 2dffffh sa92 1011100 32k words 2e00 00h to 2e7fffh sa93 1011101 32k words 2e8000h to 2effffh sa94 1011110 32k words 2f00 00h to 2f7fffh sa95 1011111 32k words 2f8000h to 2fffffh
mbm29lv650ue/651ue- 90/12 14 (continued) sector address a 21 a 20 a 19 a 18 a 17 a 16 a 15 sector size address range sa96 1100000 32k words 300000h to 307fffh sa97 1100001 32k words 3 08000h to 30ffffh sa98 1100010 32k words 310000h to 317fffh sa99 1100011 32k words 3 18000h to 31ffffh sa1001100100 32k words 320000h to 327fffh sa1011100101 32k words 3 28000h to 32ffffh sa1021100110 32k words 330000h to 337fffh sa1031100111 32k words 3 38000h to 33ffffh sa1041101000 32k words 340000h to 347fffh sa1051101001 32k words 3 48000h to 34ffffh sa1061101010 32k words 350000h to 357fffh sa1071101011 32k words 3 58000h to 35ffffh sa1081101100 32k words 360000h to 367fffh sa1091101101 32k words 3 68000h to 36ffffh sa1101101110 32k words 370000h to 377fffh sa1111101111 32k words 3 78000h to 37ffffh sa1121110000 32k words 380000h to 387fffh sa1131110001 32k words 3 88000h to 38ffffh sa1141110010 32k words 390000h to 397fffh sa1151110011 32k words 3 98000h to 39ffffh sa1161110100 32k words 3a00 00h to 3a7fffh sa1171110101 32k words 3a8000h to 3affffh sa1181110110 32k words 3b00 00h to 3b7fffh sa1191110111 32k words 3b8000h to 3bffffh sa1201111000 32k words 3c00 00h to 3c7fffh sa1211111001 32k words 3c8000h to 3cffffh sa1221111010 32k words 3d00 00h to 3d7fffh sa1231111011 32k words 3d8000h to 3dffffh sa1241111100 32k words 3e00 00h to 3e7fffh sa1251111101 32k words 3e8000h to 3effffh sa1261111110 32k words 3f00 00h to 3f7fffh sa1271111111 32k words 3f8000h to 3fffffh
mbm29lv650ue/651ue- 90/12 15 table 6 sector group address sector group address a 21 a 20 a 19 a 18 a 17 sector group size sectors sga0 0 0 0 0 0 128k words sa0 to sa3 sga1 0 0 0 0 1 128k words sa4 to sa7 sga2 0 0 0 1 0 128k words sa8 to sa11 sga3 0 0 0 1 1 128k words sa12 to sa15 sga4 0 0 1 0 0 128k words sa16 to sa19 sga5 0 0 1 0 1 128k words sa20 to sa23 sga6 0 0 1 1 0 128k words sa24 to sa27 sga7 0 0 1 1 1 128k words sa28 to sa31 sga8 0 1 0 0 0 128k words sa32 to sa35 sga9 0 1 0 0 1 128k words sa36 to sa39 sga10 0 1 0 1 0 128k words sa40 to sa43 sga11 0 1 0 1 1 128k words sa44 to sa47 sga12 0 1 1 0 0 128k words sa48 to sa51 sga13 0 1 1 0 1 128k words sa52 to sa55 sga14 0 1 1 1 0 128k words sa56 to sa59 sga15 0 1 1 1 1 128k words sa60 to sa63 sga16 1 0 0 0 0 128k words sa64 to sa67 sga17 1 0 0 0 1 128k words sa68 to sa71 sga18 1 0 0 1 0 128k words sa72 to sa75 sga19 1 0 0 1 1 128k words sa76 to sa79 sga20 1 0 1 0 0 128k words sa80 to sa83 sga21 1 0 1 0 1 128k words sa84 to sa87 sga22 1 0 1 1 0 128k words sa88 to sa91 sga23 1 0 1 1 1 128k words sa92 to sa95 sga24 1 1 0 0 0 128k words sa96 to sa99 sga25 1 1 0 0 1 128k words sa100 to sa103 sga26 1 1 0 1 0 128k words sa104 to sa107 sga27 1 1 0 1 1 128k words sa108 to sa111 sga28 1 1 1 0 0 128k words sa112 to sa115 sga29 1 1 1 0 1 128k words sa116 to sa119 sga30 1 1 1 1 0 128k words sa120 to sa123 sga31 1 1 1 1 1 128k words sa124 to sa127
mbm29lv650ue/651ue- 90/12 16 table 7 common flash memory interface code description a 0 to a 6 dq 0 to dq 15 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min. (write/erase) d7-4: volt, d3-0: 100 mvolt 1bh 0027h v cc max. (write/erase) d7-4: volt, d3-0: 100 mvolt 1ch 0036h v pp min. voltage 1dh 0000h v pp max. voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min. size buffer write 2 n m s 20h 0000h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max. timeout for byte/word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0017h flash device interface description 28h 29h 0001h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0001h erase block region 1 information 2dh 2eh 2fh 30h 007fh 0000h 0000h 0001h description a 0 to a 6 dq 0 to dq 15 erase block region 2 information 31h 32h 33h 34h 0000h 0000h 0000h 0000h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0031h address sensitive unlock 0h = required 1h = not required 45h 0001h erase suspend 0h = not supported 1h = to read only 2h = to read & write 46h 0002h sector protection 0h = not supported x = number of sectors in per group 47h 0004h sector temporary unprotection 00h = not supported 01h = supported 48h 0001h sector protection algorithm 49h 0004h number of sector for bank 2 00h = not supported 4ah 0000h burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h acc (acceleration) supply minimum 00h = not supported, d7-4: volt, d3-0: 100 mvolt 4dh 00b5h acc (acceleration) supply maximum 00h = not supported, d7-4: volt, d3-0: 100 mvolt 4eh 00c5h boot type 04h = mbm29lv651ue 05h = mbm29lv650ue 4fh 00xxh
mbm29lv650ue/651ue- 90/12 17 n n n n functional description read mode the mbm29lv650ue/651ue has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l. standby mode there are two ways to implement the standby mode on the mbm29lv650ue/651ue devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv650ue/651ue data. this mode can be used effectively with an application requesting low power consumption such as handy terminals. to activate this mode, mbm29lv650ue/651ue automatically switch themselves to low power mode when mbm29lv650ue/651ue addresses remain stable during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29lv650ue/651ue read-out the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. the autoselect command may also be used to check the status of write-protected sectors (see tables 4.1 and 4.2). this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 . (see table 2.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv650ue/651ue is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 3. (refer to autoselect command section.)
mbm29lv650ue/651ue- 90/12 18 word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code (mbm29lv650ue/651ue = 22d7h). word 3 (a 0 = a 1 = v ih ) represents the extended code (mbm29lv650ue = 2201h, mbm29lv651ue = 2200h). these three words are given in the tables 4.1 to 4.2. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 4.1 to 4.2.) in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 = 1). write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector group protection the mbm29lv650ue/651ue features hardware sector group protection. this feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (see table 6). the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il and a 0 = a 6 = v il , a 1 = v ih . the sector group addresses (a 21 , a 20 , a 19 , a 18 , and a 17 ) should be set to the sector to be protected. table 5 defines the sector address for each of the one hundred twenty-eight (128) individual sectors, and tables 2 defines the sector group address for each of the thirty-two (32) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see figures 12 and 20 for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 21 , a 20 , a 19 , a 18 , and a 17 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 21 , a 20 , a 19 , a 18 , and a 17 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see tables 4.1 and 4.2 for autoselect codes. temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the mbm29lv650ue/651ue devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to figures 13 and 21. this temporary sector group unprotect mode is disabled whenever the chip is in the hidden rom (hi-rom) mode. this area can not be programmed within this mode. moreover once this area is programmed, it is always protected no matter in which mode.
mbm29lv650ue/651ue- 90/12 19 reset hardware reset pin the mbm29lv650ue/651ue devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. write protect (wp ) the write protection function provides a hardware method of protecting certain outermost 32k word sector without using v id . if the system asserts v il on the wp pin, the device disables program and erase functions in the outermost 32k word sector independently of whether this sector was protected or unprotected using the method described in sector protection/unprotection. the outermost 32k word sector is the highest addresses in mbm29lv650ue, or the lowest addresses in mbm29lv651ue. (mbm29lv650ue: sa127, mbm29lv651ue: sa0) if the system asserts v ih on the wp pin, the device reverts to whether the outermost 32k word sector was last set to be protected or unprotected. that is, sector protection or unprotection for this sector depends on whether this was last protected or unprotected using the method described in sector protection/unprotection. accelerated program operation mbm29lv650ue/651ue offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 50%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode is not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the present sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the acc pin returns the device to normal operation. do not remove v acc from the acc pin while programming. (see figure 15.)
mbm29lv650ue/651ue- 90/12 20 n n n n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect data values or writing them in the improper sequence will reset the devices to the read mode. table 3 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the address and the autoselect command. then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from the another address. following the command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h returns the device code (mbm29lv650ue/651ue = 22d7h). a read cycle from address xx03h returns the extended code (mbm29lv650ue = 0010h, mbm29lv651ue = 0000h). (see tables 4.1 and 4.2.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address xx02h. scanning the sector group addresses (a 21 , a 20 , a 19 , a 18 , and a 17 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see table 2.) to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence.
mbm29lv650ue/651ue- 90/12 21 word programming the devices are programmed on a word-by-word basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), and dq 6 (toggle bit). the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see table 8, hardware sequence flags.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1 attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0 only erase operations can convert 0s to 1s. figure 16 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), and dq 6 (toggle bit). the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin.
mbm29lv650ue/651ue- 90/12 22 multiple sectors may be erased concurrently by writing the six bus cycle operations on table 3. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 127). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), and dq 6 (toggle bit). the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the addresses are dont care when writting the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the devices have entered the erase-suspended mode, the dq 7 bit will be at logic 1 and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .)
mbm29lv650ue/651ue- 90/12 23 after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29lv650ue/651ue has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the figure 22.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 22.) (3) extended sector group protection in addition to normal sector group protection, the mbm29lv650ue/651ue has extended sector group protection as extended function. this function enable to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , and a 17 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins), and write extended sector group protection command (60h). a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 21 , a 20 , a 19 , a 18 , and a 17 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to the figures 14 and 23.) (4) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward-compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 8 to dq 15 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register. (see table 7.)
mbm29lv650ue/651ue- 90/12 24 hidden rom (hi-rom) region the hi-rom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hi-rom region is programmed, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hi-rom region is 128 words in length. after the system has written the enter hi-rom command sequence, it may read the hidden rom region by using device addresses a 0 to a 6 (a 7 to a 14 are 00, a 15 to a 21 are dont care). that is, the device sends only program command that would normally be sent to the address to the hi- rom region. this mode of operation continues until the system issues the exit hi-rom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the address. if you request fujitsu to program the esn in the device, please contact a fujitsu representative for more information. write operation status detailed in table 8 are all the status flags that can be used to check the status of the device for current mode operation. during sector erase, the part provides the status flags automatically to the i/o ports. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows the user to determine which sectors are erasing and which are not. once erase suspend is entered, address sensitivity still applies. if the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. if the address of an erasing sector (that is, one unavailable for read) is applied, the device will output its status bits. *: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. notes: 1. dq 0 and dq 1 are reserve pins for future use. 2. dq 4 is fujitsu internal use only. table 8 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* erase suspended mode erase suspend read (erase suspended sector) 1100t oggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29lv650ue/651ue- 90/12 25 dq 7 data polling the mbm29lv650ue/651ue devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 18. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv650ue/651ue data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 8.) see figure 9 for the data polling timing specifications and diagram. dq 6 toggle bit i the mbm29lv650ue/651ue also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see figure 10 for the toggle bit i timing specifications and diagram.
mbm29lv650ue/651ue- 90/12 26 dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in table 2. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 8 : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows: for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 9 and figure 11. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector.
mbm29lv650ue/651ue- 90/12 27 *: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. data protection the mbm29lv650ue/651ue is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min). if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up. table 9 toggle bit status mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle * erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 *
mbm29lv650ue/651ue- 90/12 28 n n n n absolute maximum ratings notes: 1. minimum dc voltage on input or l/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe , acc, and reset pins is C0.5 v. during voltage transitions, a 9 , oe , acc, and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed 9.0 v. maximum dc input voltage on a 9 , oe , acc, and reset pins is +13.0 v which may overshoot to +14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note: operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses , operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min. max. storage temperature tstg C55 +125 c ambient temperature with power applied t a C40 +85 c voltage with respect to ground all pins except a 9 , oe , acc, and reset (note 1) v in , v out C0.5 v cc +0.5 v power supply voltage (note 1) v cc C0.5 +4.0 v a 9 , oe , acc, and reset (note 2) v in C0.5 +13.0 v power supply voltage v cc q C0.2 +7.0 v parameter symbol value unit min. max. ambient temperature (-90/-12) t a C40 +85 c power supply voltage (v cc ) (-90) v cc +3.0 +3.6 v (-12) +2.7 +3.6 v power supply voltage (v cc q) (-90/-12) v cc q +2.7 +3.6 v
mbm29lv650ue/651ue- 90/12 29 n n n n maximum overshoot/undershoot figure 1 maximum undershoot waveform +0.6 v C0.5 v 20 ns C2.0 v 20 ns 20 ns figure 2 maximum overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns figure 3 maximum overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note: this waveform is applied for a 9 , oe , acc , and reset .
mbm29lv650ue/651ue- 90/12 30 n n n n electrical characteristics 1. dc characteristics notes: 1. the l cc current listed includes both the dc operating current and the frequency dependent component. 2. l cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. applicable for only v cc applying. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max., v cc q = v cc q max. C1.0 +1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max., v cc q = v cc q max. C1.0 +1.0 a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe , reset = 12.5 v 35a i acc acc accelerated program current v cc = v cc max., acc = v acc max. 20ma i cc1 v cc active current (note 1) ce = v il , oe = v ih , v cc = v cc max., v cc q = v cc q max., f = 5 mhz 16ma ce = v il , oe = v ih , v cc = v cc max., v cc q = v cc q max., f = 1 mhz 7ma i cc2 v cc active current (note 2) ce = v il , oe = v ih , v cc = v cc max., v cc q = v cc q max. 40ma i cc3 v cc current (standby) v cc = v cc max., v cc q = v cc q max., ce = v cc 0.3 v, reset = v cc 0.3 v 5a i cc4 v cc current (standby, reset ) v cc = v cc max., v cc q = v cc q max., reset = v ss 0.3 v 5a i cc5 v cc current (automatic sleep mode) (note 3) v cc = v cc max., v cc q = v cc q max., ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 5a v il input low level C0.5 0.6 v v ih input high level 2.0 v cc + 0.5 v v acc voltage for program acceleration 11.5 12.5 v v id voltage for autoselect, sector protection (a 9 , oe , reset ) (note 4) 11.512.5v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min., v cc q = v cc q min. 0.45v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min., v cc q = v cc q min. 2.4 v v oh2 i oh = C100 a, v cc min., v cc q = v cc q min. v cc q C 0.4 v v lko low v cc lock-out voltage 2.3 2.5 v
mbm29lv650ue/651ue- 90/12 31 2. ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29lv650ue/651ue-90) 1 ttl gate and 100 pf (mbm29lv650ue/651ue-12) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup 90 (note) 12 (note) unit jedec standard t avav t rc read cycle time min. 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 90 120 ns t glqv t oe output enable to output delay max. 35 50 ns t ehqz t df chip enable to output high-z max. 30 30 ns t ghqz t df output enable to output high-z max. 30 30 ns t axqx t oh output hold time from address, ce or oe , whichever occurs first min. 0 0 ns t ready reset pin low to read mode max. 20 20 m s figure 4 test conditions c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w
mbm29lv650ue/651ue- 90/12 32 ? write (erase/program) operations (continued) parameter symbols description 90 12 unit jedec standard t avav t wc write cycle time min. 90 120 ns t avwl t as address setup time min. 0 0 ns t wlax t ah address hold time min. 45 50 ns t dvwh t ds data setup time min. 35 50 ns t whdx t dh data hold time min. 0 0 ns t oes output enable setup time min. 0 0 ns t oeh output enable hold time read min. 0 0 ns toggle and data polling min. 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 ns t ghel t ghel read recover time before write min. 0 0 ns t elwl t cs ce setup time min. 0 0 ns t wlel t ws we setup time min. 0 0 ns t wheh t ch ce hold time min. 0 0 ns t ehwh t wh we hold time min. 0 0 ns t wlwh t wp write pulse width min. 35 50 ns t eleh t cp ce pulse width min. 35 50 ns t whwl t wph write pulse width high min. 30 30 ns t ehel t cph ce pulse width high min. 30 30 ns t whwh1 t whwh1 word programming operation typ. 16 16 s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 s t vcs v cc setup time min. 50 50 s t vidr rise time to v id (note 2) min. 500 500 ns t vaccr rise time to v acc (note 3) min. 500 500 ns t vlht voltage transition time (note 2) min. 4 4 s t wpp write pulse width (note 2) min. 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 s t csp ce setup time to we active (note 2) min. 4 4 s t rp reset pulse width min. 500 500 ns t rh reset hold time before read min. 200 200 ns
mbm29lv650ue/651ue- 90/12 33 (continued) notes: 1. this does not include the preprogramming time. 2. this timing is for sector group protection operation. 3. this timing is for accelerated program operation. parameter symbols description 90 12 unit jedec standard t eoe delay time from embedded output enable max. 90 120 ns t tow erase time-out time min. 50 50 s t spd erase suspend transition time max. 20 20 s
mbm29lv650ue/651ue- 90/12 34 n n n n erase and programming performance n n n n pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 10 s excludes programming time prior to erasure programming time 16 360 s excludes system-level overhead chip programming time 200 s excludes system-level overhead erase/program cycle 100,000 cycle parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf c in3 acc pin capacitance v in = 0 15 20 pf
mbm29lv650ue/651ue- 90/12 35 n n n n timing diagram ? key to switching waveforms figure 5.1 read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oh t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh
mbm29lv650ue/651ue- 90/12 36 figure 5.2 hardware reset/read operation timing diagram reset t acc t oh outputs t rc addresses addresses stable high-z output valid t rh ce t rp t rh t ce
mbm29lv650ue/651ue- 90/12 37 notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. figure 6 alternate we controlled program operation timing diagram t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we xxxh pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df
mbm29lv650ue/651ue- 90/12 38 figure 7 alternate ce controlled program operation timing diagram notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce xxxh pa pa data polling 3rd bus cycle t ws t wh t ghel pd
mbm29lv650ue/651ue- 90/12 39 figure 8 chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = xxxh for chip erase. v cc ce oe addresses data t wp we xxxh xxxh xxxh xxxh xxxh sa * t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h
mbm29lv650ue/651ue- 90/12 40 figure 9 data polling during embedded algorithm operation timing diagram * : dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe t eoe we t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 data data dq 0 to dq 6 = output flag * figure 10 toggle bit i during embedded algorithm operation timing diagram * : dq 6 = stops toggling. (the device has completed the embedded operation.) ce we oe data (dq 0 to dq 7 ) dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 data valid t oe dq 6 = toggle t oeh t oes t dh dq 6
mbm29lv650ue/651ue- 90/12 41 figure 11 dq 2 vs. dq 6 dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce note: dq 2 is read from the erase-suspended sector.
mbm29lv650ue/651ue- 90/12 42 figure 12 sector group protection timing diagram sgax = sector group address for initial sector sgay = sector group address for next sector t vlht sgax a 21 , a 20 , a 19 a 18 , a 17 sgay a 0 a 6 a 9 3 v t vlht oe 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs v id v id
mbm29lv650ue/651ue- 90/12 43 3 v reset v cc ce we t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period figure 13 temporary sector group unprotection timing diagram
mbm29lv650ue/651ue- 90/12 44 figure 14 extended sector group protection timing diagram sgax: sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min) sgay reset a 6 oe we ce data a 1 v cc a 0 add sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc
mbm29lv650ue/651ue- 90/12 45 figure 15 accelerated program timing diagram 3 v acc v cc ce we t vlht program or erase command sequence 3 v t vlht t vcs t vaccr v acc t vlht acceleration period
mbm29lv650ue/651ue- 90/12 46 n n n n flow chart write program command sequence (see below) data polling program command sequence (address/command): xxxh/aah xxxh/55h xxxh/a0h program address/program data start no yes increment address last address ? programming completed embeded program algorithm in progress verify data ? no yes figure 16 embedded program tm algorithm embedded algorithms
mbm29lv650ue/651ue- 90/12 47 write erase command sequence (see below) data polling erasure completed start xxxh/aah xxxh/55h xxxh/aah xxxh/80h xxxh/10h xxxh/55h xxxh/aah xxxh/55h xxxh/aah xxxh/80h xxxh/55h additional sector erase commands are optional. chip erase command sequence (address/command): individual sector/multiple sector erase command sequence (address/command): sector address/30h sector address/30h sector address/30h data=ffh ? embeded program algorithm in progress no yes figure 17 embedded erase tm algorithm embedded algorithms
mbm29lv650ue/651ue- 90/12 48 dq 7 = data? * no no dq 7 = data? dq 5 = 1? yes yes no read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes start fail pass figure 18 data polling algorithm *dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase
mbm29lv650ue/651ue- 90/12 49 toggle bit = toggle ? yes no toggle bit = toggle ? dq 5 = 1? yes no no yes start *1,*2 *1 read dq 7 to dq 0 twice read dq 7 to dq 0 program/erase operation not complete.write reset command program/erase operation complete read dq 7 to dq 0 figure 19 toggle bit algorithm *1:reset toggle bit twice to determine whether or not it is toggle. *2:recheck toggle bit because it may stop toggle as dq5 changes to 1 .
mbm29lv650ue/651ue- 90/12 50 setup sector group addr. (a 21 , a 20 , a 19 , a 18 , a 17 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector group (addr. = sga, a 0 = v il , a 1 = v ih , a 6 = v il ) remove v id from a 9 write reset command increment plscnt no yes protect another sector group ? data = 01h? plscnt = 25? remove v id from a 9 write reset command start sector group protection completed device failed figure 20 sector group protection algorithm
mbm29lv650ue/651ue- 90/12 51 reset = v id * 1 perform erase or program operations reset = v ih start temporary sector group unprotection completed * 2 figure 21 temporary sector group unprotection algorithm *1: all protected sector groups are unprotected. *2: all previously protected sector groups are protected once again.
mbm29lv650ue/651ue- 90/12 52 to sector group protection yes no no plscnt = 1 protection other sector start sector group protection extended sector group completed remove v id from reset write reset command reset = v id wait to 4 m s protection entry? to setup sector group protection write xxxh/60h write sga/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 250 m s to verify sector group protection write sga/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? group? device is operating in temporary sector group read from sector group (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt no yes yes unprotection mode address setup next sector group address no yes plscnt = 25? device failed remove v id from reset write reset command figure 22 extended sector group protection algorithm
mbm29lv650ue/651ue- 90/12 53 figure 23 embedded program tm algorithm for fast mode fast mode algorithm start xxxh/aah xxxh/55h xxxh/a0h xxxh/20h verify data? no program address/program data data polling device last address ? programming completed xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode
mbm29lv650ue/651ue- 90/12 54 n n n n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29lv650u(651u) e 90 tn device number/description mbm29lv650u(651u) 64 mega-bit (4m 16-bit) cmos flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e tn= 48-pin thin small outline package (tsop) standard pinout tr = 48-pin thin small outline package (tsop) reverse pinout speed option see product selector guide device revision
mbm29lv650ue/651ue- 90/12 55 n n n n package dimensions (continued) c 2000 fujitsu limited f48029s-3c-4 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 11.50ref (.453) 0.50(.0197) typ 0.20?.10 (.008?004) 0.10?.05 .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (.004?002) 1 24 25 48 lead no. * * 12.00?.20 (.472?008) (mounting height) 0.10(.004) (stand off) dimensions in mm (inches) 48-pin plastic tsop (i) (fpt-48p-m19) *: resin protrusion. (each side: 0.15(.006) max)
mbm29lv650ue/651ue- 90/12 56 (continued) c 2000 fujitsu limited f48030s-3c-4 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 11.50(.453)ref 0.50(.020) typ 0.20?.10 (.008?004) .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) 1 24 25 48 lead no. * * 12.00?.20(.472?008) (mounting height) 0.10(.004) 0.10?.05 (.004?002) (stand off) dimensions in mm (inches) 48-pin plastic tsop (i) (fpt-48p-m20) *: resin protrusion. (each side: 0.15(.006) max)
mbm29lv650ue/651ue- 90/12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0012 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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